One-mask mtj integration for stt mram

ABSTRACT

A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit includes providing in a semiconductor back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer and at least a first conductive interconnect. Over the first interlevel dielectric layer and the first conductive interconnect, magnetic tunnel junction material layers are deposited. From the material layers a magnetic tunnel junction stack, coupled to the first conductive interconnect, is defined using a single mask process. The magnetic tunnel junction stack is integrated into the integrated circuit.

CROSS REFERENCE TO RELATED APPLICATION

This application claims priority to provisional application No.61/046,517, entitled “ONE-MASK MTJ INTEGRATION FOR STT MRAM,” by SeungH. Kang, et al., filed Apr. 21, 2008, which claims priority to U.S.Publication 2009-0261433 A1, Published Oct. 22, 2009, which is expresslyincorporated herein by reference in its entirety.

TECHNICAL FIELD

This disclosure relates to integrated electronic circuitry, and inparticular, to spin transfer torque (STT) magnetic random access memory(MRAM) and methods of integration with standard integrated circuitry.

BACKGROUND

Unlike conventional random access memory (RAM) chip technologies, inmagnetic RAM (MRAM) data is not stored as electric charge, but bymagnetic polarization of storage elements. The elements are formed fromtwo magnetically polarized plates, each of which can maintain a magneticpolarization field, separated by a thin insulating layer, which togetherform a magnetic tunnel junction (MTJ). One of the two plates is apermanent magnet (hereinafter “fixed layer”) set to a particularpolarity; the polarization of the other plate (hereinafter “free layer”)will change to match that of a sufficiently strong external field. Amemory device may be built from a grid of such “cells”.

Reading the polarization state of an MRAM cell is accomplished bymeasuring the electrical resistance of the cell's MTJ. A particular cellis (conventionally) selected by powering an associated transistor whichswitches current from a supply line through the MTJ to a ground. Due tothe tunneling magnetoresistance effect, the electrical resistance of thecell changes due to the relative orientation of the polarizations in thetwo magnetic layers of the MTJ. By measuring the resulting current, theresistance inside any particular cell can be determined, and from thisthe polarity of the free writable layer determined. If the two layershave the same polarization, this is considered to mean State “0”, andthe resistance is “low,” while if the two layers are of oppositepolarization the resistance will be higher and this means State “1”.

Data is written to the cells using a variety of schemes. In conventionalMRAM, an external magnetic field is provided by current in a wire inproximity to the cell, which is strong enough to align the free layer.

Spin-transfer-torque (STT) MRAM uses spin-aligned (“polarized”)electrons to directly torque the domains of the free layer. The currentto write to the cells through this mechanism is less than the writecurrent for conventional MRAM. Furthermore, no external magnetic fieldis required, so that adjacent cells are substantially unaffected bystray fields. This write current further decreases as the memory cellsize scales down, which is a critical benefit as the semiconductortechnology continues to scale to higher device pitch density.

One significant determinant of a memory system's cost is the density ofthe components on the chip. Smaller components, and fewer components per“cell,” mean that more “cells” may be packed onto a single chip, whichin turn means more chips can be produced at once from a singlesemiconductor wafer and fabricated at lower cost and improved yield.

In addition, the manufacturing process flow affects cost, with more maskprocesses contributing to increased overall manufacturing costs. Whenfabrication of conventional MRAM requires a number of mask processesdedicated solely to the fabrication of the magnetic tunnel junction(MTJ) structure, costs are further increased. Because processing cost isa serious consideration in implementing integration of features in anintegrated circuit device, any improvement in the design and processflow that eliminates masks and associated processes is advantageous. Adifference in one mask process can save significant costs. Accordingly,a need exists for improved methods for integrating MRAM fabrication inthe semiconductor manufacturing process flow. Moreover, any design thatrelaxes alignment of critical dimension features would be desirable.

SUMMARY

A method of integrating fabrication processes and a structure of amagnetic random access memory (MRAM) magnetic tunnel junction (MTJ) intostandard back-end-of-line (BEOL) integrated circuit manufacturingincludes a single photo mask.

In an aspect, a method integrates a magnetic tunnel junction (MTJ)device into an integrated circuit. The method includes providing in asemiconductor back-end-of-line (BEOL) process flow a substrate having afirst interlevel dielectric layer and at least a first metalinterconnect. The method also includes depositing over the firstinterlevel dielectric layer and the first metal interconnect multiplemagnetic tunnel junction material layers. The method further includesdefining from the material layers a magnetic tunnel junction stackcoupled to the first metal interconnect using a single mask process. Themagnetic tunnel junction stack is integrated into the integratedcircuit.

In another aspect, a magnetic tunnel junction device is in an integratedcircuit (IC) including at least a magnetic random access memory (MRAM).The device includes a substrate having a first metal interconnect; aswell as a magnetic tunnel junction stack communicating with the firstmetal interconnect. The magnetic tunnel junction stack was defined usinga single mask process. The device also includes a second metalinterconnect in communication with the magnetic tunnel junction stack.The magnetic tunnel device is integrated into the IC.

In yet another aspect, a magnetic tunnel junction (MTJ) structure formagnetic random access memory (MRAM) includes a first interconnect meansfor communicating with at least one control device; and a firstelectrode means for coupling to the first interconnect means. The devicealso includes an MTJ means for storing data, and a second electrodemeans for coupling to the MTJ means. The MTJ means couples to the firstelectrode means. The first and second electrode means have a samelateral dimension as the MTJ means based upon a first mask. The devicefurther includes a second interconnect means for coupling to the secondelectrode means and at least one other control device.

The foregoing has outlined rather broadly the features and technicaladvantages of the present disclosure in order that the detaileddescription of embodiments of the disclosure that follows may be betterunderstood. Additional features and advantages of the embodiments willbe described hereinafter which form the subject of the claims of thedisclosure. It should be appreciated by those skilled in the art thatthe conception and specific embodiments disclosed may be readilyutilized as a basis for modifying or designing other structures forcarrying out the same purposes of the present disclosure. It should alsobe realized by those skilled in the art that such equivalentconstructions do not depart from the spirit and scope of the disclosureas set forth in the appended claims. The novel features which arebelieved to be characteristic of the disclosure, both as to itsorganization and method of operation, together with further objects andadvantages will be better understood from the following description whenconsidered in connection with the accompanying figures. It is to beexpressly understood, however, that each of the figures is provided forthe purpose of illustration and description only and is not intended asa definition of the limits of the present disclosure.

DESCRIPTION OF FIGURES

For a more complete understanding of the present disclosure, referenceis now made to the following descriptions taken in conjunction with theaccompanying drawings.

FIG. 1 shows an exemplary wireless communication system in whichembodiments of the disclosure may be advantageously employed.

FIG. 2 is a block diagram illustrating a design workstation used forcircuit, layout, logic design and integration of MRAM in a semiconductorback-end-of-line (BEOL) process flow, in accordance with an embodimentof the disclosure.

FIG. 3 is a cross section view showing an embodiment of an MTJ structuredefined with a single mask process.

FIG. 4 is a schematic process flow for forming an MTJ structure that maybe imbedded in a single damascene semiconductor back-end-of-line (BEOL)process flow, according to an embodiment of the disclosure.

FIG. 5 is a schematic process flow for forming an MTJ structure that maybe imbedded in a dual damascene semiconductor back-end-of-line (BEOL)process flow, according to an embodiment of the disclosure.

FIGS. 6A and 6B are cross section views showing a dielectric barrier ona substrate, and an intermediate structure for forming an MTJ structureincluding a dielectric barrier, respectively, according to anotherembodiment of the disclosure.

DETAILED DESCRIPTION

A magnetic tunnel junction (MTJ) device and method of forming the sameinclude a single photomask process. In one embodiment, the MTJ andmethod of forming pertain to MRAM. In another embodiment, the MTJ andmethod of forming can pertain to spin-torque-transfer (STT) MRAM.

A method of making and a structure for a magnetic tunnel junction devicefor MRAM based on a single mask process may be imbedded within aback-end-of-line (BEOL) process flow in order to integrate MRAM memoryincluding, but not limited to, STT MRAM, in standard semiconductorprocesses. Additional other masks and processes, such as may be used todefine elements for interconnection to the disclosed device may be apart of the BEOL process flow.

FIG. 1 shows an exemplary wireless communication system 100 in which anembodiment of the disclosure may be advantageously employed. Forpurposes of illustration, FIG. 1 shows three remote units 120, 130, and150 and two base stations 140. It will be recognized that conventionalwireless communication systems may have many more remote units and basestations. Remote units 120, 130, and 150 include MRAM and/or STT MRAMmemory devices 125A, 125B and 125C, which are embodiments of thedisclosure as discussed further below. FIG. 1 shows forward link signals180 from the base stations 140 and the remote units 120, 130, and 150and reverse link signals 190 from the remote units 120, 130, and 150 tobase stations 140.

In FIG. 1, remote unit 120 is shown as a mobile telephone, remote unit130 is shown as a portable computer, and remote unit 150 is shown as afixed location remote unit in a wireless local loop system. For example,the remote units may be mobile phones, hand-held personal communicationsystems (PCS) units, portable data units such as personal dataassistants, navigation devices (e.g., GPS enabled devices,) set-topboxes, music players, video players, entertainment units, fixed locationdata units such as meter reading equipment, or any other device thatstores or retrieves data or computer instructions, or any combinationthereof. Although FIG. 1 illustrates remote units according to theteachings of the disclosure, the disclosure is not limited to theseexemplary illustrated units. Embodiments of the disclosure may besuitably employed in any device which includes a magnetic memory.

FIG. 2 is a block diagram illustrating a design workstation used forcircuit, layout, and logic design of the disclosed semiconductorintegrated circuit. A design workstation 200 includes a hard disk 201containing operating system software, support files, and design softwaresuch as CADENCE or ORCAD. The design workstation 200 also includes adisplay 202 to facilitate design of a circuit design 210. The circuitdesign 210 may be the memory circuit as disclosed above. A storagemedium 204 is provided for tangibly storing the circuit design 210. Thecircuit design 210 may be stored on the storage medium 204 in a fileformat such as GDSII or GERBER. The storage medium 204 may be a CD-ROM.DVD, hard disk, flash memory, or other appropriate device. Furthermore,the design workstation 200 includes a drive apparatus 203 for acceptinginput from or writing output to the storage medium 204.

Data recorded on the storage medium 204 may specify logic circuitconfigurations, pattern data for photolithography masks, or mask patterndata for serial write tools such as electron beam lithography. The datamay further include logic verification data such as timing diagrams ornet circuits associated with logic simulations. Providing data on thestorage medium 204 facilitates the design of the circuit design 210 bydecreasing the number of processes for designing semiconductor ICs.

In this disclosure a device and a method of making MRAM devices within aBEOL process are provided that utilizes only one mask to form an MTJ.This enables a potentially large reduction in the cost of imbeddingmemory in an integrated circuit product.

FIG. 3 is a cross-section of a magnetic tunnel junction devicefabricated with a single mask process embedded in a currentback-end-of-line (BEOL) process. The formation of the MTJ stack iscompatible with standard back-end-of-line (BEOL) process flows. The MTJstack formation occurs after transistor fabrication, which is commonlyreferred to as a front-end-of-line (FEOL) process flow.

In terms of structure, the MTJ device has all the same layers requiredto provide MTJ functionality, and uses the same materials as aconventional MTJ device. However, the process is simplified compared tothe processes required to fabricate the conventional MTJ device, whichmay rely on more masks and processes.

Referring to FIG. 3, an MTJ stack is formed over a planarized surfacethat includes a first metal interconnect 37 and a first interleveldielectric (ILD) 36. The stack includes a first electrode 2, a fixedmagnetization reference layer 32, a tunnel barrier 12, a free layer 11,and a second electrode 6. In one embodiment, the fixed magnetizationreference layer 32 includes a fixed antiferromagnetic layer and asynthetic antiferro-magnetic layer, neither of which are shown.

A conventional dielectric barrier between the first ILD 36 and the firstcontact layer 2 is absent. To compensate for the loss of theconventional dielectric barrier, the first electrode 2 may be arefractory metal such as, for example, tantalum (Ta). The first metalinterconnect 37 may commonly be copper, and tantalum may be used as anexcellent barrier material for blocking diffusion of copper intoadjacent layers. In other words, tantalum blocks diffusion of metals,such as copper, from the first metal interconnect 37, eliminating theneed for the conventional dielectric barrier. Additionally, depositing atantalum layer on top of the first ILD 36 and first metal interconnect37 is a process friendly integration scheme common to complementarymetal oxide semiconductor (CMOS). The second electrode 6 may be the samematerial as the first electrode 2, but is not limited to such material.

The stack and the first ILD 36 are protected by a deposited firstdielectric passivation barrier 8. A second ILD 40 is also deposited tosufficiently fill in the surrounding area. When the dielectricpassivation barrier 8 and second ILD 40 are planarized, the secondelectrode 6 is exposed.

The second ILD 40 may also contain a metal via 41 to connect one of thefirst metal interconnects 37 (in level n (on the right side of thefigure)) with a second metal interconnect 39 (in level n+1). In oneembodiment, forming such “bypass” via is a part of the BEOL processflow, and does not impact the formation of the MTJ structure.

A dielectric passivation barrier 7 and a third ILD 34 can then bedeposited over the planarized surface. A third metal interconnect 35 maybe formed in the second dielectric passivation barrier 7 and the thirdILD 34 to connect the electrode 6 of the stack to circuitry that may belater formed above the third ILD 34. The second metal interconnect 39can be formed in the second dielectric passivation barrier 7 and thethird ILD 34 to connect the “bypass” via 41 to circuitry that may belater formed above the third ILD 34. In one embodiment, the third metalinterconnect 35 is a bit line interconnect and the first metalinterconnect 37 links an MTJ to a source line through an accesstransistor.

The second dielectric passivation barrier 7 and the first dielectricbarrier 8 may be formed from dense insulating materials such as, forexample, SiC or SiN. The first and second electrodes 2 and 6 may beformed from refractory metals such as tantalum, as previously mentioned.The metal interconnect 37, second metal interconnect 39 and third metalinterconnect 35 may be formed from metals such as copper or other lowresistivity metals.

Small dimensions present a challenge when aligning the single MTJ stackformed by the one mask with the first metal interconnect 37 and thethird metal interconnect 35. However, successfully aligning to acritical dimension in a single mask process enables a potentiallysignificant reduction in process costs relative to process with multiplemasks. In various embodiments, the dimensions of the first metalinterconnect 37 and third metal interconnect 35 may be smaller, the sameor greater than the dimensions of the MTJ stack. In the case where thefirst metal interconnect 37 and third metal interconnect 35 are larger,the alignment critical dimension is substantially moot.

FIG. 4 shows a schematic process flow for forming an MTJ device that maybe imbedded in a single damascene semiconductor BEOL process flow,according to an embodiment of the disclosure.

Process 1: Beginning with a planarized surface that includes the metalinterconnect 37 and the first ILD 36, a succession of layers aredisposed on the surface, including material for the first electrode 2,the magnetic reference layer 32, the tunnel barrier layer 12, themagnetic free layer 11, and the second electrode 6. It is noted that nodielectric barrier layer is present between the first electrode 2 andthe layer including the metal interconnect 37 and the first ILD 36.

As seen in process 2, a single mask is used to define the shape andfabricate a stack of magnetic tunnel junction films by etching thelayers 6, 11, 12, 32 and 2 which were deposited, as described above.

In process 3, the dielectric passivation barrier 8 is disposed over theentire surface, including the MTJ stack, the ILD 36 and the metalinterconnect 37. The dielectric passivation layer 8 protects thecomponents and can also act as an etch stop for future etching.

Process 4: The ILD layer 40 is deposited and encapsulates the devicelevel containing the MTJ stack. The ILD 40 both encapsulates the MTJstack and the passivation barrier 8 and provides structure for formationof “bypass” metal-filled vias, such as the via 41 to connect circuitry,e.g., between components in a BEOL level on one side of the MTJ stack(e.g., level n), and components in a BEOL level on the other side of theMTJ stack (e.g., level n+1), in the process flow, as indicated in FIG.3.

Process 5: A portion of the ILD 40 and a portion of passivation barrier8 may be removed by planarization to level and expose the secondelectrode 6 and the via 41 provided within the ILD 40. Alternatively,the via 41 may be deposited after planarization. In other words a holeis created in the ILD 40 and the hole is then filled to form the via 41.Further planarization levels the via 41.

Process 6: A dielectric passivation barrier 7 is deposited and an ILD 34is deposited over the dielectric passivation barrier 7. Metalinterconnect 35 is formed in the dielectric passivation barrier 7 andthe ILD 34 to contact the second electrode 6 and metal interconnect 39is formed to couple to the via 41 between the two adjacent BEOL levels(i.e., between the level including the metal interconnect 37 and thelevel including the metal interconnects 35 and 39).

The processes shown in FIG. 4 illustrate an example when using a singledamascene semiconductor BEOL process. Description will now be providedof a dual damascene semiconductor BEOL process, according to anotherembodiment of the disclosure. Processes 1-4 in FIG. 5 are identical toprocesses 1-4 in FIG. 4. Process 5 for the dual damascene embodimentdiffers in that the trenches to be filled with metal to form the metalinterconnects 35 and 39 and the bypass via 41 are formed first.Subsequently, metal is deposited into the trenches in the ILD 34, thedielectric passivation barrier 7 and the ILD 40 at the same time. Thestructure resulting from the dual damascene process (as shown in FIG. 5,process 6) is identical to the structure resulting from the singledamascene process (as shown in process 6 of FIG. 4).

FIG. 6A shows another embodiment, in which a barrier layer 60 is formedover the ILD 36, prior to fabricating the metal interconnect 37. Thebarrier layer 60 acts as an etch stop and as a barrier to protect theILD 36. As seen in FIG. 6B, in this embodiment the MTJ material layers2, 32, 12, 11, 6 are deposited over the barrier 60 in the first MTJfabrication process. The MTJ integration processes may then proceed asdescribed above.

An advantage of the methods and devices described above is that thesingle mask MTJ process is compatible with and can be integrated withboth single and dual damascene processes, both of which are common toBEOL process flows in integrated circuit manufacturing. A single maskprocess reduces fabrication costs and complexity relative toconventional MTJ fabrication. The entire MTJ can be formed with the samedimension as the first electrode 2, enabling a tighter device pitch andlower contact resistance. Where the dimensions of the MTJ stack and themetallization interconnects 37 and/or 35 are appropriately chosen,critical dimension alignment criteria may be eased.

Where the MTJ device is for STT MRAM, the device is scalable to smallerdimensions. The compatibility with nano-scale fabrication enables lowercost and higher device density fabrication of STT MRAM memory chips withscaling.

MRAM as set forth in the disclosure may operate with logic circuitrysuch as microprocessors. The MRAM may be integrated into devices thatemploy the microprocessors. For example, the MRAM may be part of acommunications device. Of course the MRAM may include other types ofcircuitry without departing from the scope and spirit of the disclosure.

Although the embodiments of the present disclosure and its advantageshave been described in detail, it should be understood that variouschanges, substitutions and alterations can be made herein withoutdeparting from the spirit and scope of the disclosure as defined by theappended claims. Moreover, the scope of the present application is notintended to be limited to the particular embodiments of the process,machine, manufacture, composition of matter, means, methods and stepsdescribed in the specification. As one of ordinary skill in the art willreadily appreciate from the disclosure of the present disclosure,processes, machines, manufacture, compositions of matter, means,methods, or steps, presently existing or later to be developed thatperform substantially the same function or achieve substantially thesame result as the corresponding embodiments described herein may beutilized according to the present disclosure. Accordingly, the appendedclaims are intended to include within their scope such processes,machines, manufacture, compositions of matter, means, methods, or steps.

What is claimed is:
 1. A magnetic tunnel junction (MTJ) device in anintegrated circuit (IC), comprising: a substrate comprising a firstinterlevel dielectric layer and a first conductive interconnect; and amagnetic tunnel junction stack communicating with the first conductiveinterconnect, the magnetic tunnel junction stack comprising a pluralityof magnetic tunnel junction material layers directly on the firstinterlevel dielectric layer and the first conductive interconnect, themagnetic tunnel junction stack having been defined from all of theplurality of magnetic tunnel junction material layers using only asingle mask process, wherein the magnetic tunnel device is integratedinto the IC.
 2. The MTJ device of claim 1, wherein the magnetic tunneljunction stack comprises: a first electrode layer directly on the firstconductive interconnect and on the first interlevel dielectric layer;the plurality of magnetic tunnel junction layers on the first electrodelayer; and a second electrode on the magnetic tunnel junction layers. 3.The MTJ device of claim 2, wherein the magnetic tunnel junction layerscomprise: a fixed magnetization layer; a tunnel barrier layer; and afree magnetization layer.
 4. The MTJ device of claim 2, furthercomprising: a first dielectric passivation barrier layer on the magnetictunnel junction stack and directly on the first interlevel dielectriclayer; and a second interlevel dielectric layer on the first dielectricpassivation barrier layer, the second interlevel dielectric layer andthe first dielectric passivation barrier layer exposing the secondelectrode of the magnetic tunnel junction stack.
 5. The MTJ device ofclaim 4, further comprising: a second dielectric passivation barrierlayer on the second interlevel dielectric layer and the secondelectrode; a third interlevel dielectric layer on the second dielectricpassivation barrier layer; and a second conductive interconnect in thethird interlevel dielectric layer and the second dielectric passivationbarrier layer, the second conductive interconnect being in communicationwith the second electrode.
 6. The MTJ device of claim 5, furthercomprising: a third conductive interconnect in the first interleveldielectric layer; a conductive via in the second interlevel dielectriclayer and the first dielectric passivation barrier layer, the conductivevia being in communication with the third conductive interconnect; and afourth conductive interconnect in the third interlevel dielectric layerand the second dielectric passivation barrier layer, the fourthconductive interconnect being in communication with the conductive via.7. The MTJ device of claim 1, further comprising a barrier layer betweena first interlevel dielectric of the substrate and the magnetic tunneljunction stack.
 8. The MTJ device of claim 1, wherein the MTJ device isincorporated in a device selected from the group consisting of a mobilephone, personal data assistant (PDA), navigation device, fixed locationdata unit, set-top box, music player, video player, entertainment unit,and computer.
 9. A magnetic tunnel junction (MTJ) structure, comprising:a substrate comprising a first interlevel dielectric layer and a firstconductive interconnect; and means for communicating with the firstconductive interconnect, the means for communicating with the firstconductive interconnect comprising a plurality of magnetic tunneljunction material layers directly on the first interlevel dielectriclayer and the first conductive interconnect, the communicating meansdefined from all of the plurality of magnetic tunnel junction materiallayers using only a single mask process.
 10. The MTJ structure of claim9, wherein the communicating means comprises a magnetic tunnel junctionstack comprising: a first electrode layer directly on the firstconductive interconnect and on the first interlevel dielectric layer;the plurality of magnetic tunnel junction layers on the first electrodelayer; and a second electrode layer on the magnetic tunnel junctionlayers.
 11. The MTJ structure of claim 10, wherein the magnetic tunneljunction layers comprise: a fixed magnetization layer; a tunnel barrierlayer; and a free magnetization layer.
 12. The MTJ structure of claim10, further comprising: a first dielectric passivation barrier layer onthe magnetic tunnel junction stack and directly on the first interleveldielectric layer; and a second interlevel dielectric layer on the firstdielectric passivation barrier layer, the second interlevel dielectriclayer and the first dielectric passivation barrier layer exposing thesecond electrode layer of the magnetic tunnel junction stack.
 13. TheMTJ structure of claim 12, further comprising: a second dielectricpassivation barrier layer on the second interlevel dielectric layer andthe second electrode layer; a third interlevel dielectric layer on thesecond dielectric passivation barrier layer; and a second conductiveinterconnect in the third interlevel dielectric layer and the seconddielectric passivation barrier layer, the second conductive interconnectin communication with the second electrode layer.
 14. The MTJ structureof claim 13, further comprising: a third conductive interconnect in thefirst interlevel dielectric layer; a conductive via in the secondinterlevel dielectric layer and the first dielectric passivation barrierlayer, the conductive via being in communication with the thirdconductive interconnect; and a fourth conductive interconnect in thethird interlevel dielectric layer and the second dielectric passivationbarrier layer, the fourth conductive interconnect being in communicationwith the conductive via.
 15. The MTJ structure of claim 9, furthercomprising a barrier layer between a first interlevel dielectric of thesubstrate and the means for communicating.
 16. The MTJ structure ofclaim 10 in which the first electrode layer and the second electrodelayer have a same lateral dimension as the magnetic tunnel junctionstack based upon a first mask.
 17. The MTJ structure of claim 16,integrated into a spin-torque-transfer (STT) MRAM.
 18. The MTJ structureof claim 17, in which the STT MRAM is coupled to a microprocessor. 19.The MTJ structure of claim 17, in which the STT MRAM is integrated intoa device selected from the group consisting of a set top box, musicplayer, video player, entertainment unit, navigation device,communications device, personal digital assistant (PDA), fixed locationdata unit, microprocessor, and a computer.
 20. The MTJ structure ofclaim 9, incorporated in a device selected from the group consisting ofa mobile phone, personal data assistant (PDA), navigation device, fixedlocation data unit, set-top box, music player, video player,entertainment unit, and computer.
 21. A magnetic tunnel junction (MTJ)structure, comprising: a first conductive interconnect arranged tocouple with at least one control device; a first electrode layer on thefirst conductive interconnect; a magnetic tunnel junction stackcomprising a plurality of magnetic tunnel junction material layers onthe first electrode layer; a second electrode layer on the magnetictunnel junction stack, the first electrode layer and the secondelectrode layer having a same lateral dimension as the magnetic tunneljunction stack based upon a first mask; and a second conductiveinterconnect on the second electrode layer and arranged to couple withat least one other control device.
 22. The MTJ structure of claim 21,integrated into a spin-torque-transfer (STT) magnetic random accessmemory (MRAM).
 23. The MTJ structure of claim 22, in which the STT MRAMis coupled to a microprocessor.
 24. The MTJ structure of claim 22, inwhich the STT MRAM is integrated into a device selected from the groupconsisting of a set top box, music player, video player, entertainmentunit, navigation device, communications device, personal digitalassistant (PDA), fixed location data unit, microprocessor, and acomputer.
 25. A magnetic tunnel junction (MTJ) structure, comprising: afirst interconnect means for communicating with at least one controldevice; a first electrode means for coupling to the first interconnectmeans; an MTJ means for storing data, the MTJ means coupling to thefirst electrode means; a second electrode means for coupling to the MTJmeans, the first and second electrode means having a same lateraldimension as the MTJ means based upon a first mask; and a secondinterconnect means for coupling to the second electrode means and atleast one other control device.
 26. The MTJ structure of claim 25,integrated into a spin-torque-transfer (STT) MRAM.
 27. The MTJ structureof claim 26, in which the STT MRAM is coupled to a microprocessor. 28.The MTJ structure of claim 26, in which the STT MRAM is integrated intoa device selected from the group consisting of a set top box, musicplayer, video player, entertainment unit, navigation device,communications device, personal digital assistant (PDA), fixed locationdata unit, microprocessor, and a computer.